1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device having a nonvolatile semiconductor memory.
2. Description of the Related Art
EEPROMs are known as semiconductor memories, for example, nonvolatile semiconductor memories. Some EEPROMs have wells whose potential can be changed and memory cell transistors formed on the wells. As a representative example thereof, a flash memory, for example, a NAND flash memory in which data in a plurality of memory cell transistors are simultaneously erased is provided.
Each memory cell transistor of the NAND flash memory has a charge storage layer, for example, a floating gate. The level of the threshold voltage of the memory cell transistor varies according to the amount of charge stored in the floating gate. Data is set and stored according to the level of the threshold voltage.
When data is erased in the NAND flash memory, positive potential is applied to a well called a cell well. Further, when data is written or read out, the potential of the cell well is set to zero, for example.
Thus, the potential of the cell well of the NAND flash memory is changed according to the operation thereof. Therefore, the cell well is connected to a cell well bias circuit which applies the potential corresponding to the operation to the cell well. The potential generated from the cell well bias circuit is supplied to a memory cell array via a cell well bias line and applied to the cell well via a cell well contact. Some cell well lines are laid out parallel to bit lines in the memory cell array, for example, and some cell well contacts are arranged under the cell well bias lines in the memory cell array.
Wiring bodies such as the bit lines, word lines, block selection lines and floating gates are laid out in a repetitive form in the memory cell array. However, the repetitive arrangement cannot be maintained in the portions of the cell well bias lines and cell well contacts. A NAND flash memory having a layout pattern in which the repetitive arrangement is partially lost is described in Jpn. Pat. Appln. KOKAI Publication No. 2000-91546.